Low cost shallow trench isolation using non-conformal dielectric material

ABSTRACT

A method is provided for planarizing a structure such as a shallow trench isolation region on a semiconductor substrate. A semiconductor substrate is provided having raised and lowered regions with substantially vertical and horizontal surfaces. The lowered regions may correspond to trench regions. Filler material such as non-conformal high density plasma oxide may be deposited over the horizontal surfaces to at least a thickness equal to a predetermined height so as to provide raised and lowered regions of the filler material. The raised regions of the filler material may then be selectively removed without removing the filler material in the lowered regions.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention generally relates to a process to formplanarized shallow trench isolation structures using a non-conformalhigh density plasma (HDP) oxide deposition.

[0003] 2. Description of the Related Art

[0004] Integrated circuits are formed from semiconductor substrateswithin and upon whose surfaces are formed resistors, transistors, diodesand other electrical circuit elements. The electrical circuit elementsare connected internally and externally to the semiconductor substrateupon which they are formed through patterned conductor layers which areseparated by dielectric layers.

[0005] As integrated circuit device technology has advanced andintegrated circuit device dimensions have decreased, it has becomeincreasingly common within advanced integrated circuits to employ trenchisolation methods such as shallow trench isolation (STI) methods andrecessed oxide isolation (ROI) methods to form trench isolation regionsnominally co-planar with adjoining active semiconductor regions ofsemiconductor substrates. Such trench isolation methods typically employa chemical mechanical polish (CMP) planarizing method to provide anominally planarized surface to a trench isolation region formed from atrench fill dielectric layer formed within the trench. Trench isolationregions nominally co-planar with active semiconductor regions withinsemiconductor substrates are desirable since they optimize, whensubsequently forming patterned layers upon those nominally co-planartrench isolation regions and active semiconductor regions, the limiteddepth of focus typically achievable with advanced photoexposure.

[0006] Two major challenges in achieving the shallow trench isolation(STI) structure are: (1) filling the narrow trenches without voids orseams defect, and (2) planarization of trenches of diverse widths.Conventional STI processes may employ conformal low pressure chemicalvapor deposition (LPCVD) TEOS deposition and a complicated planarizationprocess which uses two step photoresist coating, reactive ion etch (RIE)etch back and chemical mechanical polish (CMP). Due to the nature ofconformal LPCVD TEOS deposition, seams are generally present in theLPCVD TEOS filled shallow trench isolation region. The seams become amajor problem as the device dimensions scale downward and the aspectratio of the STI increases.

SUMMARY OF THE INVENTION

[0007] In view of the foregoing and other problems of the conventionalmethods, it is, therefore, an object of the present invention to providea method for planarizing a structure on a semiconductor substrate. Themethod may include providing the semiconductor substrate having raisedand lowered regions with substantially vertical and horizontal surfaces.The vertical surfaces may have a predetermined height. Further, themethod may include depositing filler material over the horizontalsurfaces to at least a thickness equal to the predetermined height so asto provide raised and lowered regions of the filler material. The methodmay also include selectively removing the raised regions of the fillermaterial.

[0008] The filler material may be non-conformal high density plasma(HDP) oxide. Additionally, the lowered regions of filler material may becovered with a mask and the filler material on the raised regions may beetched. The raised regions may not be protected by the mask.

[0009] An oxide pad and a nitride pad may be provided on thesemiconductor substrate. The raised and lowered regions may be formed bymasking regions of the nitride pad and etching exposed areas of thenitride pad. The oxide pad and the nitride pad may be further removedafter selectively removing the raised regions of the filler material.Further, only the raised regions of the filler material are etchedwithout etching the lowered regions of the filler material.

[0010] Other objects, advantages and salient features of the inventionwill become apparent from the following detailed description taken inconjunction with the annexed drawings, which disclose preferredembodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The invention will be described in detail with reference to thefollowing drawings in which like reference numerals refer to likeelements and wherein:

[0012] FIGS. 1-6 show cross section views of the STI filled withnon-conformal HDP oxide according to the present invention;

[0013]FIG. 7 shows a cross section view of the planarized STI structure;

[0014]FIG. 8 shows a flowchart of a preferred method of the presentinvention;

[0015] FIGS. 9-11 show steps of planarization according to the presentinvention; and

[0016]FIG. 12 shows a flowchart according to the method shown in FIGS.9-11.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION

[0017]FIG. 1 shows a preferred method of forming a shallow trenchisolation (STI) region using non-conformal dielectric material such asnon-conformal high density plasma oxide. In this method, a siliconsubstrate 10 is initially provided and an oxide pad 30 and a nitride pad40 are then formed over silicon substrate 10. A trench region 20 is thenformed into the silicon substrate 10 in a conventional manner. Normallythe trench region 20 is delineated by 1) applying a thin coat ofphotoresist on the wafer, 2) exposing selected regions of thephotoresist to light in order to induce a chemical change in thephotoresist, and 3) removing the exposed portions of the photoresist bywet-chemical means. Then the exposed regions of the wafer are removed toa desired depth using an anisotropic subtractive etch process.Conventional and appropriate subtractive etch methods include reactiveion etching, which is also known as plasma etching or dry etching. Suchan etch process normally exhibits high uniformity, high selectivity tothe photoresist or other masking material, and high directionality(anisotropy).

[0018] A filler material preferably formed of non-conformal high densityplasma oxide 50 is provided over the entire silicon substrate and in thetrench region 20 using a conventional deposition process. Pure silicondioxide is preferably used, although doped oxides containing smallamounts of phosphorous or boron may also be used. Further, fluorine maybe useful for lowering the dielectric constant of the isolation. Ingeneral, any material which can be made in the form shown in the figuresand is also useful as a trench isolation material can be used. Thepreferred material properties include good gap-fill, low dielectricconstant, high purity, and thermal and chemical stability in thepresence of other semiconductor device materials. As shown in FIG. 1,the oxide material in the trench 50 b should be very uniform andslightly thicker than the depth of the trench region 20. The fillermaterial at the upper edge of the trench 50 c should also be of uniformthickness, and preferably on the order of the thickness of the nitridefilm 40 or thinner. The invention can accommodate some variation in thethickness and sidewall-profile of the non-trench oxide material 50 a.

[0019] Unlike conventional methods, the non-conformal dielectricmaterial, such as the high density plasma oxide, fills the trench region20 without any seams defect. That is, HDP oxides can be made to haveexcellent gap-fill characteristics because the extra energy available ina high-density plasma system allows the balance in the competitionbetween etching and deposition to be finely adjusted. In practice, abalance is struck that allows deposition to occur much more effectivelyon horizontal surfaces than on vertical ones. For example, argonbombardment knocks off the oxide formed on vertical surfaces andredeposits it on horizontal surfaces in the trench region 20. Thissputter/deposition method achieves a non-conformal seams-free trenchfill. For HDP oxide, this same balance between etching and depositionleads to the other features of the trench fill that are important to theinvention.

[0020] The oxide 50 fills the trench region 20 to a predeterminedheight, which will be maintained throughout the entire planarizationprocess. This predetermined height is preferably greater than a depth ofthe trench region 20 as measured from the bottom of the trench region 20to a bottom of the oxide pad 30. As is known in the art, if the trenchstructure were made entirely of oxide, and that oxide were bombardedwith high-energy ions as are present in a physical-sputtering tool (orin a high-density plasma deposition tool) then the exposed comers ofoxide would quickly become beveled, generally at a 45-degree angle. Thisoccurs because the atoms on the exposed comer are the easiest todislodge. Under the right circumstances, the oxide that gets knocked offthe exposed comers can collect in the interior comers at the bottom ofsmall trenches. These things all occur at once in a typical HDP oxidedeposition process. That is, oxide material tends to deposit everywhereuniformly, but is preferentially knocked off the sides of existingvertical surfaces in the substrate (allowing for excellent gap-fill) andoff of the growing shoulder at the upper edge of these surfaces to formthe sloped, beveled edges in the raised portion of the oxide.

[0021] Before the photoresist is applied to the wafer surface andpatterned, the deposited filler material is etched slightly, as shown inFIG. 2. This etch step is performed in order to remove all of thatportion of the filler material 50 c shown in FIG. 1, which acts toexpose the pad nitride 40 in those regions. In other words, the upperpart of the oxide is separated from the oxide in the trench region 20after a short pull-back DHF (or BHF ) oxide etch. An equal amount offilms 50 a and 50 b are likewise removed by the etch process, which forsimplicity has been illustrated as an isotropic or non-directional etch.This etching results in a structure similar to that shown in FIG. 2.That is, the trench oxide 50 b is completely separated from thenon-trench oxide 50 a, and the pad nitride 40 is the only materialexposed between those regions.

[0022]FIG. 3 shows an encapsulation photo resist 60 which is appliedover the trench region 20 to protect the oxide 50 within the trenchregion 20. This photo resist 60 can be any film that can be patternedand is resistant to oxide etching. The encapsulation photo resist 60protects the high density plasma oxide 50 within the trench region 20and maintains the oxide 50 at the predetermined height while theremaining high density plasma oxide 50 is etched away in a well-knownmanner, as shown in FIG. 4. Any subtractive etch that is selective tophoto resist 60 and pad film 40 (normally nitride) will suffice. An etchprocess that is largely isotropic is beneficial, but etch isotropy isnot a necessary feature. A hydrofluoric-acid containing wet-etch ispreferred, because it is quick, cheap, selective to nitride and photoresist, and it is isotropic. This last characteristic allows portions ofthe oxide 50 a that are partially covered by photo resist 60 to also beetched away. The high selectivity to nitride and photo resist allows theoxide filler material 50 b to be protected from the etchant, by virtueof the intimate contact between nitride 40 and photo resist 60 at allupper edges of the isolation trenches. Creating and maintaining a tightseal at these interfaces is important. Any small, narrow regions ofnon-trench oxide 50 a that are completely covered by photo resist 60 canbe accommodated by the subsequent processing. Such regions might ormight not be present on a wafer surface, depending on the specificmorphology of the HDP deposit and whether restrictions are placed on thedesign to prohibit them. After the exposed regions of the non-trenchoxide 50 a are removed, the photo resist 60 is removed by conventionalmeans.

[0023]FIG. 5 shows the result of the etching process in which the highdensity plasma oxide 50 a in the non-trench regions has been removed,except possibly for small, narrow, isolated regions as depicted.Accordingly, the etching removes all of the HDP oxide 50 that is notprotected by the encapsulation photo resist 60 and then theencapsulation photo resist 60 is removed. The nitride pad 40 is nextremoved, as shown in FIG. 6. Small quantities of dopant species areoften implanted into the silicon substrate 10 through the pad oxide 30before the pad oxide 30 is removed. The pad nitride 40 is preferablyremoved by subtractive etch. A phosphoric-acid containing wet-etch iscommon. The pad nitride 40 is used as a buffer film to protect theraised regions of the silicon (where the semiconductor devicesthemselves are to be built) during the trench isolation fabricationprocess. Once the isolation trenches have been formed, filled andplanarized, the pad nitride 40 is preferably removed to allow for theshallow implantation of trace dopants to effect the desired electricalbehavior in the subsequent semiconductor devices. After implantation,the pad oxide 30 is normally removed and a very thin, very high-purityoxide is grown on the exposed raised portions of the silicon substrate10. This thin oxide becomes the “transfer gate oxide” that covers the“channel region” of the semiconductor “switches”.

[0024]FIG. 7 shows the resulting STI structure formed using thenon-conformal high density plasma oxide 50. As discussed above, theresulting STI is seamless due to the non-conformal HDP oxide 50.

[0025]FIG. 8 shows a flowchart of the method according to the presentinvention for forming the STI using the non-conformal high densityplasma 50. In step S100, the oxide pad 30 and nitride pad 40 areprovided on the semiconductor substrate 10. The trench region 20 is thenformed in step S102. The non-conformal high density plasma oxide 50 isdeposited over the entire semiconductor substrate 10 including thetrench region 20 and the non-trench regions in step S104. The depositedtrench-fill material is etched slightly in step S105 to expose the padnitride 40 all along the boundary between trench oxide 50 b andnon-trench oxide 50 a. The trench region 20 is masked in step S106 andthe high density plasma oxide 50 is removed from the non-masked regionswhich are the non-trench regions. This is preferably accomplished usingthe encapsulation photo resist 60. In step S108, the encapsulation photoresist 60 is removed. Subsequently, in step S110, the nitride pad 40 andoxide pad 30 are removed resulting in the planarized STI.

[0026] FIGS. 9-11 show an additional embodiment of forming theplanarized STI and FIG. 12 shows a corresponding flowchart. In thisembodiment, the oxide pad 30 and nitride pad 40 are formed on thesemiconductor substrate 10 in step S100 and the trench regions 20 aresubsequently formed in step S102. In a similar manner, the high densityplasma oxide 50 is applied in step S104, and the oxide film is etchedback in step S105, in order to expose the nitride pad 40 at the edges ofthe trench regions in a similar manner to that shown in FIG. 2. Then, instep S112, a conformal film such as a silicon nitride film 80 is appliedover the deposited high density plasma oxide 50, as shown in FIG. 9. Instep S114, the conformal film 80 is sputter-etched so as to exposeportions of each discrete piece of the non-trench high-density plasmaoxide film 50 b at exposed comers, such as at regions X, Y and Z shownin FIG. 10. Physical sputtering processes are well-known to be able topreferentially remove material from exposed comers such as X, Y and Z.Subsequently, in step S116, the overburden of the non-trench highdensity plasma oxide 50 a is removed using an isotropic etch processthat is highly selective to the conformal film 80 and to the nitride pad40 as shown in FIG. 11. A wet etchant containing hydrofluoric acid ispreferred because it is quick, cheap, selective to nitride, and it isisotropic. Finally, in step S118, the remainder of the conformal film 80is removed along with the pad nitride film 40 using an isotropic etchprocess that is highly selective to the pad oxide and to the remaininghigh density plasma oxide 50 b. A phosphoric-acid containing wet-etch iscommonly used for this purpose. If a small, narrow region of non-trenchoxide material 50 a (such as region Z in FIG. 9) is not exposed by thesputter-etch (or similar) process in step S114, then they will remain onthe wafer after the isotropic oxide etch of step S116. But as suchremaining regions of oxide 50 a are small, if they exist at all, theywill float off the wafer as they are undercut by the isotropic nitrideetch in step S118. This results in the planarized STI structure shown inFIG. 6. As in the previous embodiment, further processing to remove theoxide pad 30, according to step S118, results in the fully planarizedstructure depicted in FIG. 7.

[0027] This invention results in a novel, yet very simple process toform a planarized STI structure using non-conformal high density plasma(HDP) oxide deposition and photo resist encapsulation planarization.This has at least three major advantages as compared with conventionalSTI processes. First, this invention eliminates many process stepsemployed by the current STI process such as photo resist planarization,reactive ion etching (RIE), etch back and CMP. Second, a non-conformaldielectric material such as high density plasma (HDP) oxide fills thetrenches without any seams defect. All RIE and CMP related defects suchas particulate contamination, CMP scratches and chatter markers may beeliminated using the present invention. Third, the present inventionachieves uniform local and global planarization without adding anyconstraints to RX mask layout.

[0028] While the invention has been described with reference to specificembodiments, the description of the specific embodiments is illustrativeonly and is not to be considered as limiting the scope of the invention.Various other modifications and changes may occur to those skilled inthe art without departing from the spirit and scope of the invention.

What is claimed is:
 1. A method of planarizing a structure on asemiconductor substrate, the method comprising: providing saidsemiconductor substrate with raised and lowered regions withsubstantially vertical and horizontal surfaces, said vertical surfaceshaving a predetermined height; depositing filler material over saidhorizontal surfaces to at least a thickness equal to said predeterminedheight so as to provide raised and lowered regions of filler material;and selectively removing said raised regions of said filler material. 2.The method of claim 1 , wherein said filler material comprisesnonconformal high density plasma oxide.
 3. The method of claim 1 ,wherein adjacent sections of said raised and lowered regions of fillermaterial are separated by at least a gap of exposed underlying materialand the selectively removing comprises covering said lowered regions offiller material with a mask and etching said filler material on saidraised regions which are not protected by said mask.
 4. The method ofclaim 1 , further comprising covering said lowered regions of fillermaterial with a conformal coating, and wherein said selectively removingcomprises removing said coating from substantially all of said raisedregions, and etching said filler material on said raised regions,wherein during said selectively removing adjacent sections of said upperand lower regions of filler material are separated by at least a gap ofexposed underlying material.
 5. The method of claim 1 , furthercomprising providing an oxide pad on said semiconductor substrate andproviding a nitride pad on said oxide pad, wherein said raised andlowered regions are formed by masking regions of the nitride pad andetching exposed areas of said nitride pad.
 6. The method of claim 5 ,further comprising removing said oxide pad and said nitride pad afterselectively removing said raised regions of said filler material.
 7. Themethod of claim 1 , wherein the selectively removing comprisesselectively etching only said raised regions of said filler materialwithout etching said lowered regions of said filler material.
 8. Asemiconductor substrate having a planarized trench region formedaccording to the method of claim 1 .
 9. A method for planarizing atrench region provided in a semiconductor substrate, the methodcomprising: providing the semiconductor substrate with at least onetrench region; applying a filler material in the trench region and onthe semiconductor substrate; and removing only said filler materialwhich is not provided in said trench region.
 10. The method of claim 9 ,wherein said filler material comprises non-conformal high density plasmaoxide.
 11. The method of claim 9 , wherein the removing comprisescovering the trench region with a mask and etching said filler materialfrom regions which are not protected by said mask.
 12. The method ofclaim 9 , further comprising covering said trench region with aconformal coating, and wherein said removing comprises removing saidcoating from substantially all non-trench regions and etching saidfiller material on the non-trench regions.
 13. The method of claim 9 ,further comprising providing an oxide pad on said semiconductorsubstrate and providing a nitride pad on said oxide pad, wherein said atleast one trench region is formed by masking regions of said nitride padand etching exposed areas of said nitride pad.
 14. The method of claim 9, further comprising removing said oxide pad and said nitride pad afterremoving the filler material which is not provided in the trench region,wherein adjacent sections of said trench regions and non-trench regionsof filler material are separated by at least a gap of exposed underlyingmaterial.
 15. A semiconductor substrate having a planarized trenchregion formed according to the method of claim 9 .
 16. A method offorming a planarized structure on a semiconductor substrate, the methodcomprising: providing the semiconductor substrate with a trench regionand non-trench regions; depositing filler material on said trench regionand said non-trench regions, said filler material filling said trenchregion to a predetermined height; and removing said filler material fromsaid non-trench regions while allowing said filler material in saidtrench region to remain filled to the predetermined height.
 17. Themethod of claim 16 , wherein said filler material comprisesnon-conformal high density plasma oxide.
 18. The method of claim 16 ,wherein adjacent sections of said trench region and non-trench region offiller material are separated by at least a gap of exposed underlyingmaterial and the removing comprises covering said trench regions offiller material with a mask and etching said filler material on saidnon-trench regions which are not protected by said mask.
 19. The methodof claim 16 , wherein the removing comprises covering said trenchregions of filler material with a conformal coating, and wherein saidremoving comprises removing said coating from substantially all of saidnon-trench regions, and etching said filler material on said non-trenchregions, wherein during the removing adjacent sections of said trenchregion and non-trench region of filler material are separated by atleast a gap of exposed underlying material.
 20. The method of claim 16 ,further comprising providing an oxide pad on said semiconductorsubstrate and providing a nitride pad on said oxide pad, wherein saidtrench region and the non-trench regions are formed by masking regionsof said nitride pad and etching exposed areas of said nitride pad. 21.The method of claim 20 , further comprising removing said oxide pad andsaid nitride pad after removing said filler material on the non-trenchregions.
 22. The method of claim 16 , wherein the removing comprisesselectively etching said filler material on the non-trench regionswithout etching said filler material on the trench regions.
 23. Asemiconductor substrate having a planarized structure formed accordingto the method of claim 16 .